Recent improvements for transistors have involved the use of multiple gate devices. By using a three dimensional structure as the channel of a transistor and forming a gate overlying more than one surface of the channel region, the gate width may be increased without a corresponding increase in silicon area. Evolution of these multiple gate transistors led to the development of finFET devices which have a gate portion overlying a fin that includes a source and drain region, and a channel. In a finFET the gate forms over the two vertical sides and the horizontal top portion of the fin, increasing the gate width substantially over a similar sized planar metal-oxide-semiconductor (MOS) FET.
Further increases in performance have been achieved using a gate-all-around structure for the FET. In this approach, gate material is formed on all sides of a rectangular, elliptical or cylindrical channel region with adjacent source and drain regions. Silicon nanowires, for example, are surrounded by a gate dielectric and an overlying gate conductor on all sides. In forming a gate-all-around FET, a semiconductor portion may be subjected to oxidation to form an oxide. Defects in this oxide can lead to leakage problems, and reduced oxide performance.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.